The present invention relates to a nonvolatile semiconductor memory device and an optimizing programming method thereof, and more particularly to a EEPROM having NAND-structured cells and a method capable of optimizing the data programming using the same.
FIG. 1 is a plan view showing a conventional NAND-structured cell string of the first generation, and an equivalent circuit thereof. FIG. 2 shows control voltage conditions during a read operation and the timing of the control voltage during erasing and programming operations of a flash memory having the NAND structured cell string of the first generation.
The operating condition of a selected cell while erasing and programming in the conventional flash memory of first generation is as follows. First, while erasing, by supplying an erase voltage (17 V) to the gate CL6 of a selected cell CL6, and 0 V to the drain of the cell, electrons are injected from the drain to a floating gate by F-N (Fowler-Nordheim) tunneling, so that the cell's threshold voltage becomes positive.
While programming, by supplying 0 V to the gate of selected cell CL6 and a program voltage (22 V) to its drain, electrons are emitted from the floating gate to the drain of the cell by F-N tunneling, so that the threshold voltage of the cell becomes negative (refer to IEEE Journal of Solid-State Circuits, Oct. 1989, pp. 1238-1243). Therefore, while erasing and programming, stress is continuously imposed on the thin gate oxide layer for tunneling at the drain-side of the cell, which affects endurance (the number of write cycles) and data retention (the charge retention characteristic of a floating gate) of the cell. In particular, if the cell size is increasingly scaled down by achieving higher densities and larger capacitances, the above-described reliable characteristic of the cell is further degraded.
FIGS. 3A and 3B are schematic sectional views of a cell for illustrating the erasing and programming operations of a flash memory having a conventional NAND-structured cell of the second generation.
In the flash memory of the second generation, while erasing (FIG. 3A), 0 V is supplied to a gate CG of a selected cell, and an erase voltage (20 V) is supplied to a substrate SU, a source S, and a drain D, so that electrons are emitted from a floating gate FG of the cell to substrate SU, which makes the threshold voltage of the cell negative. While programming (FIG. 3B), a program voltage (20 V) is applied to gate CG of the selected cell, and 0 V is supplied to substrate SU, source S and drain D, so that electrons are injected from substrate SU to floating gate FG of the cell, which makes the threshold voltage of the cell positive. That is, the operational condition is contrary to that of the flash memory of the first generation, and the injection and emission of electrons are not limited to the cell's drain, but occur throughout its floating gate, substrate, source as well as the drain. Therefore, leakage current through the thin gate oxide layer for tunneling which is caused by stress during erasing and programming can be decreased, thereby greatly enhancing reliability of the cell. In addition to this, the threshold voltage of the cell is negative during erasing, and the problem of over-erasing is solved (refer to Symposium on VLSI Technology/1990, pp. 129 and 130).
However, as shown in FIG. 4A, since the threshold voltage distribution characteristic of the programmed cell degrades due to high voltage variations caused by the variation of process parameters during the cell programming in the flash memory of the second generation, an over-programming phenomenon occurs. In other words, even if only one cell is over-programmed within a cell string of a NAND-structured flash memory, the entire cell string is not read out. Accordingly, some means for preventing over-programming is required to maintain the optimized programming condition.
When the programming is repeated via program verification as shown in FIG. 4B, it can be noted that the threshold voltage of a cell is evenly distributed.
Thus, conventionally, programmed data states of a flash EEPROM are verified and the re-programming of data is carried out by an external verifying controller which performs the algorithm shown in FIG. 5, in order to optimize data programming. The data program verification algorithm loads data in a page mode and latches input data. Then, after programming the latched data into each cell of a selected cell line, data is read out to verify the programmed state of the data. When the read-out data is the same as an expected value, programming is completed. Meanwhile, when the read-out data differs from the expected value, as shown in FIG. 6, data bits corresponding to a cell which has failed in the programming of a "1" are maintained at "1," and data bits corresponding to a cell into which a data bit "1" or "0" is normally programmed are set to zero. The data processed as described above is repeatedly adjusted in the page mode, and the adjusted data is re-programmed into each cell of the selected cell-line. After repeating the programming, the data is read out to check the programmed state of each cell, so that the programming operation is finished when the programming is in the normal state. Otherwise, the cycling process of reading out data and programming the corrected data is repeated as described above when the programming is in an abnormal state (refer to IEEE Journal of Solid-State Circuits, April 1991, pp. 492-496).
However, according to the foregoing conventional verification algorithm, the process wherein data programmed by an external controller is read out and checked, and then loaded again for re-programming should be repeatedly carried out until the normal programmed state of every cell is detected, which degrades the performance of the overall system.